Quadruple Gate Spin–FET: A Novel Approach to Power–Efficient Reconfigurable Logic Design Beyond CMOS

This work presents a compact electrical model of a quadruple-gate spin field-effect transistor (QGSFET) for power-efficient and reconfigurable logic beyond conventional CMOS technology. The proposed device exploits independent multi-gate control to realize both two-operand and three-operand logic functions using a common channel length, thereby providing enhanced functional flexibility without requiring separate device geometries for different logic operations. The QGSFET is modeled in Verilog-A and implemented in the Cadence simulation environment, where we systematically evaluate its electrical characteristics and switching behavior through DC and transient analyses across different channel lengths. The proposed multi-gate configuration enables reconfigurable implementations of AND, NAND, OR, NOR, XOR, XNOR, three-input XNOR, Majority Gate, and Complementary Majority Gate functions, demonstrating the versatility of the device for compact logic design. A 1-bit full adder and a 2-bit binary adder are further developed using QGSFET-based logic. Comparative evaluation with conventional CMOS and previously reported Spin-FET-based implementations demonstrates reductions in device count, power consumption, propagation delay, and energy consumption, together with improved area efficiency. The results establish the QGSFET as a promising device architecture for low-power, compact, and reconfigurable nanoscale logic circuits, highlighting its potential for beyond-CMOS computing applications.

This work is significant because it introduces a quadruple-gate spin field-effect transistor (QGSFET) architecture for compact, energy-efficient, and reconfigurable logic beyond conventional CMOS technology. Independent gate control enables multiple two-input and three-input logic functions without structural modifications, reducing hardware complexity. The demonstrated adder circuits highlight its potential for arithmetic processing with improved area efficiency, lower power consumption, and reduced propagation delay. These findings provide a promising theoretical foundation for developing flexible nanoscale computing architectures and next-generation low-power digital systems.

This study presents a Verilog-A model of a quadruple-gate spin field-effect transistor implemented in Cadence for DC and transient analysis. By controlling independent gate voltages and varying channel length, the device supports AND, NAND, OR, NOR, XOR, XNOR, majority, and complementary majority functions. QGSFET-based one-bit full adders and two-bit binary adders demonstrate its arithmetic capabilities. Comparative evaluations indicate improvements in device count, power consumption, propagation delay, energy efficiency, and area utilization relative to conventional CMOS and earlier spin-FET configurations.