Design and Analysis of an Interleaved Dual - Buck Full - Bridge Transformerless Inverter with Active Common-Mode Voltage Clamp for Photovoltaic Applications

Transformerless photovoltaic (PV) inverters have emerged as the preferred solution for grid-connected residential and commercial systems owing to their reduced size, lower cost, and improved efficiency achieved by eliminating the line-frequency transformer. However, the absence of galvanic isolation introduces common-mode (CM) leakage current through the parasitic capacitance between the PV array and the grounded module frame, leading to safety concerns, electromagnetic interference, and reduced system reliability. This paper presents the design and analysis of an interleaved dual-buck full-bridge (IDBFB) transformerless inverter incorporating an active common-mode voltage clamp (ACMVC) to mitigate residual CM voltage and suppress leakage current. The proposed topology employs two interleaved buck converters operating at 40 kHz for high-frequency power processing, while a 50 Hz unfolding full-bridge generates the grid-frequency AC output, thereby inherently reducing CM voltage variations. To eliminate the residual CM voltage generated during buck-converter dead-time intervals, an ACMVC comprising two back-to-back MOSFETs, a blocking capacitor, and a simple NOR-gate-based control circuit is introduced to clamp the buck-output node to the DC-link midpoint. A 1 kW, 230 V RMS, 50 Hz prototype system is designed and modelled in MATLAB/Simulink to evaluate the proposed control strategy. Simulation results verify correct PWM generation, interleaved converter operation, synchronized unfolding-bridge switching, and effective clamp activation during dead-time intervals, demonstrating the feasibility of the proposed approach for reducing common-mode disturbances. The presented work establishes a practical design framework for transformerless PV inverters and provides a foundation for future experimental validation of leakage current, total harmonic distortion, conversion efficiency, and compliance with grid-interconnection standards.

This study addresses a critical challenge in transformerless photovoltaic inverters: common-mode (CM) voltage and leakage current caused by parasitic capacitance between the PV array and grounded frame. The proposed interleaved dual-buck full-bridge inverter with an active common-mode voltage clamp provides an effective approach to suppress residual CM voltage during converter dead-time intervals. By combining interleaved high-frequency power processing with active clamping, the proposed design offers a practical framework for improving safety, electromagnetic compatibility, reliability, and overall performance of transformerless grid-connected PV systems.

The study presents the design and MATLAB/Simulink modelling of a 1 kW, 230 V RMS, 50 Hz interleaved dual-buck full-bridge transformerless PV inverter incorporating an active common-mode voltage clamp. Two interleaved buck converters operate at 40 kHz, while a 50 Hz unfolding full-bridge produces the AC output. A back-to-back MOSFET-based clamp with a blocking capacitor and NOR-gate control suppresses residual CM voltage during dead-time intervals. Simulation results confirm proper PWM operation, interleaving, synchronized switching, and effective clamp activation.