Experimental Validation of a Self - Timed Active Common - Mode Voltage Clamp in a 1 kW Interleaved Dual - Buck Transformer - less PV Inverter

Removing the isolation transformer from a grid-connected photovoltaic (PV) inverter raises efficiency but leaves the parasitic capacitance of the array exposed to the common-mode voltage of the inverter. This paper reports the hardware validation of a 1 kW interleaved dual-buck full-bridge inverter with an active common-mode voltage clamp (IDBFB-ACMVC). Two 40 kHz buck legs interleaved by 180° shape a rectified sine, a 50 Hz insulated-gate bipolar transistor (IGBT) bridge unfolds it, and two anti-series MOSFETs with a 100 nF film capacitor join the buck output to the DC-link midpoint whenever neither buck switch is on. The clamp is switched by a NOR of the gate commands already generated for the two buck switches, so it uses no pulse-width modulation (PWM) channel of its own and carries no load current. The prototype was brought up in stages, from a perfboard unfolding bridge to a single printed circuit board with a dsPIC33 controller and gate drivers matched to the reference node and switching rate of each switch. From a 380 V DC bus, with a 100 nF capacitor emulating the array capacitance, the clamp reduces the measured leakage current from 46.4 mA to 9.6 mA RMS (79.3%), 3.1 times below the 30 mA threshold of VDE 0126-1-1. Efficiency peaks at 96.7% at 700 W and is 95.9% at 1 kW, voltage and current total harmonic distortion are 1.99% and 3.54%, and the power factor exceeds 0.99. Separating the measured leakage into its 100 Hz floor and its dead-time drift shows that the clamp removes about 81% of the drift.

This work is significant because it demonstrates, through hardware validation, a practical means of reducing common-mode leakage current in transformerless grid-connected photovoltaic inverters while preserving high efficiency. Its novelty lies in the interleaved dual-buck full-bridge topology with an active common-mode voltage clamp that is implemented without a dedicated PWM channel, instead using a NOR logic signal derived from existing gate commands so that the clamp carries no load current. Scientifically, the study clarifies how the clamp influences leakage-current behavior by showing that it suppresses the drift component associated with dead time and substantially lowers the total measured leakage current under realistic operating conditions. The key contributions are the staged prototype development, the integration of the clamp with appropriately referenced gate drivers and a dsPIC33 controller, and the experimental confirmation of improved electrical performance, including high efficiency, low harmonic distortion, and unity-like power factor. Potential applications include transformerless PV inverters and other grid-connected power converters where leakage-current mitigation, compliance with safety limits, and efficiency retention are simultaneously required.

The study presents and experimentally validates a 1 kW interleaved dual-buck full-bridge photovoltaic inverter with an active common-mode voltage clamp to reduce leakage current in transformerless grid-connected systems. The inverter uses two 40 kHz interleaved buck legs to form a rectified sine wave, a 50 Hz IGBT bridge to unfold it, and an auxiliary clamp made of two anti-series MOSFETs and a 100 nF film capacitor. The clamp is driven by a NOR of the existing buck gate signals, so it requires no extra PWM channel and carries no load current. A prototype was developed in stages and implemented on a single PCB with dsPIC33 control and appropriately referenced gate drivers. Tests with a 380 V DC bus and a capacitor simulating PV array parasitic capacitance showed that the clamp reduced RMS leakage current from 46.4 mA to 9.6 mA, a 79.3% reduction, bringing it well below the 30 mA VDE 0126-1-1 limit. The inverter achieved up to 96.7% efficiency at 700 W and 95.9% at 1 kW, with low THD (1.99% voltage, 3.54% current) and power factor above 0.99. Analysis also showed that the clamp removed about 81% of the leakage-current drift caused by dead time.